Buffer circuits are circuits having an output similar to their input, but where shape and/or amplitude deformations likely to affect the input have been corrected. Buffer circuits thus enable adjusting the level of a signal which might otherwise be wrongly interpreted if no buffer was used. The buffers considered herein enable one to transform a high input impedance into a low output impedance.
In the case of buffers intended to power a capacitive load, problems may appear if the capacitive load has a high value and if the signal to be transmitted also has a high frequency. Indeed, in this case, the capacitive load may not have time to charge/discharge and thus to switch state on each state switching of the circuit input. To avoid this, the circuits are generally provided so that the capacitive load placed at the circuit output has a rise and fall time on the order of a bit transmission time. For a transmission to be of good quality, sufficient detection times of the high or low states at the output of a buffer must, however, be provided.
FIG. 1 shows a known buffer receiving, on an input terminal OUT1, a signal originating from the output of a data processing circuit (not shown). The circuit of FIG. 1 comprises, between two terminals of a power supply voltage (in the shown example, a first terminal at a high voltage VDD and a second terminal at a low voltage VSS), a series association, starting from the terminal of highest voltage (VDD), of a P-channel MOS transistor P1, a first resistor of variable value R1, a second resistor of variable value R2, and an N-channel MOS transistor N1. The gate of transistor P1 is connected to a node A of application of a voltage for controlling transistor P1 and the gate of transistor N1 is connected to a node B of application of a voltage for controlling transistor N1. The buffer output, OUT2, is connected to the connection node between resistors R1 and R2. The values of resistors R1 and R2 are generally provided to have equal resistances on either side of output OUT2, between power supply terminals VDD and VSS when transistors P1 and N1 are on (the on-state resistances of transistors P1 and N1 being most often different). Output OUT2 powers a capacitive load C (shown in dotted lines in FIG. 1).
Input terminal OUT1 of the circuit is connected to a first input terminal of a first control circuit PR1 having its output connected to node A, and to a first input terminal of a second control circuit PR2 having its output connected to node B. Control circuits PR1 and PR2 further receive, on a second input terminal, a signal EN for enabling the circuit. Control circuits PR1 and PR2 are provided to transmit an instruction on the gates of transistors P1 and N1 to turn on one or the other of these transistors, and thus to connect output OUT2 alternately to high voltage VDD or to low voltage VSS, according to the value of input and enable signals OUT1 and EN.
Enable signal EN may be in a first state when the circuit is not being used, for example, during phases when it is known that no data transmission is carried out. In this case, circuits PR1 and PR2 turn off transistors P1 and N1. When the circuit is being used (signal EN in a second state) and input voltage OUT1 is in the high state, control circuit PR1 forces the voltage at node A to zero. This turns on transistor P1 and connects output OUT2 to voltage VDD. Meanwhile, control circuit PR2 imposes a voltage at node B in the low state, to turn off transistor N1. Conversely, when input signal OUT1 is low, the voltages at nodes A and B are high.
FIG. 2 illustrates curves of the signal on output OUT2 according to different values of input OUT1 over a duration equal to two bit times (approximately 2 ns). This specific timing diagram shape is conventionally called an eye diagram. In the example of FIG. 2, a capacitive load C of approximately 10 pF is connected to output OUT2 and the data transmission frequency is on the order of 530 MHz. Conventionally, “bit time” designates half the data transmission period, when the transmit system is used in double data rate (DDR). For a data transmission frequency on the order of 530 MHz, the bit time is thus slightly shorter than one nanosecond.
In the curves illustrated in FIG. 2, a first set of curves 10 for which the value of output VOUT2 remains constant and equal to VDD, in the shown example, to 1.2 V, may first be observed. This first set of curves illustrates the case where input OUT1 remains in the high state for several bit times. A second set of curves 12 corresponding to an output voltage VOUT2 equal to low power supply voltage VSS, that is, in the shown example, equal to 0 V, may also be observed. This second set of curves illustrates the case where input OUT1 remains in the low state for several bit times.
A third set of curves 14 corresponds to the signal on output OUT2 in the case where, before a time t=0, input OUT1 is in the low state, then switches to the high state for the entire shown duration, that is, for two bit times. In this case, the curve of output OUT2 follows the charge curve of a capacitor of high value, that is, at the end of the first bit time (t≈1 ns), the capacitor at the output of the circuit of FIG. 1 is not fully charged (VOUT2<VDD). Symmetrically, a fourth set of curves 16 corresponds to the case where, before time t=0, input OUT1 is in the high state, and then switches to the low state for at least two bit times. In this case, curves 16 follow the discharge curve of a capacitor of high value, that is, at the end of the first bit time, the capacitor is not fully discharged (VOUT2>VSS).
A fifth set of curves 18 corresponds to the case where the capacitor is initially discharged at time t=0, after which input OUT1 switches to a high state, and then to a low state in the next two bit times. In this case, the capacitor charges to a certain point at the end of the first bit time, then discharges. It should be noted that, in this case, the maximum value reached by output voltage VOUT2 is lower than high power supply voltage VDD. Symmetrically, a sixth set of curves 20 shows the case where input OUT1 switches from a high state to a low state, then back to a high state. In this case, voltage VOUT2 does not reach the low voltage of power supply VSS and reaches at least a value on the order of 0.2 V.
Thus, according to the past state of voltage VOUT2, different curves appear. Further, in a same set of curves, slight differences appear. Such differences are also due to the past of the circuit, for example to the duration for which the circuit input is in a first state before proceeding to a second state.
Based on the curves illustrated in FIG. 2, several parameters enabling one to qualify the quality of the transmission obtained by the circuit of FIG. 1 are defined. Indeed, for the output state on output terminal OUT2 to be clearly determinable by a circuit placed downstream of the circuit of FIG. 1, the voltage on output OUT2, in the high state or in the low state, must be able to be detected during a relatively long time. The circuit placed downstream of the circuit of FIG. 1 generally comprises comparators of voltage VOUT2 with high and low reference voltages.
In the example of FIG. 2, a high detection voltage equal to 0.9 V in the shown example, has been called V+, and a low detection voltage, equal to 0.3 V in the shown example, has been called V−. When the voltage on output terminal OUT2 is between V+ and V−, no detection can be performed. When voltage VOUT2 is greater than V+, a high state is detected, and conversely, when voltage VOUT2 is smaller than voltage V−, a low state is detected.
To qualify the quality of a buffer, the minimum duration for which a logic ‘1’ or ‘0’ can be measured is called an “eye opening”. In the example of FIG. 2, this duration corresponds to the duration for which, in the critical case of curves 18, a ‘1’ can be detected (duration T1) and, in the opposite case, for critical curves 20, to minimum time T2 for which a ‘0’ can be detected at the circuit output. The larger the eye opening (T1 and T2), the better the quality of the transmission and the buffer.
The circuit jitter, corresponds to a duration T3 between the time when a first one of the curves of FIG. 2 switches from average power supply value (VDD−VSS)/2 and the time when the last curve switches to this same value during a bit time. The lower the jitter of a circuit, the less chances there are for data to be poorly detected at the circuit output.
FIGS. 3A, 3B, and 3C are timing diagrams respectively illustrating an input signal OUT1 and signals corresponding to node A (VA) and to node B (VB) provided by control circuits PR1 and PR2, in the case where the circuit is enabled (signal EN does not influence control circuits PR1 and PR2). When input voltage OUT1 changes value, voltages VA and VB also change values with a given delay not shown in the timing diagrams of FIGS. 3A to 3C. Preferably, the signals at nodes A and B do not abruptly switch values but exhibit constant slopes before reaching the final value to avoid large current surges in the power supply branch of the load placed on output OUT2 at the powering-on of transistor P1 and N1.
There is a need for a buffer capable of powering a capacitive load of high value having a low jitter and a large eye opening.